The present invention relates to the field of phase lock loops. Specifically, the present invention relates to a method for reducing the power up time of a phase lock loop.
A phase lock loop (PLL) circuit is a circuit that is used for the synchronization of signals or for multiplying or dividing an input clock signal. For example, PLLs can function as synchronizing circuits in which an output frequency is synchronized or locked to a reference frequency. PLLs are used in a wide variety of electronic circuits where signals containing analog and digital information are decoded. They may be used in optical tachometers, motor control, television receivers, disk drives, modems, radios, and many other fields. PLLs may also be used in mobile communication applications related to such purposes as frequency generation, signal modulation and demodulation, and data decoding and encoding.
PLLs are unsynchronized when they have no reference signal. In this condition the PLLs are said to be unlocked or out of lock. PLLs generally work by comparing an input or a reference frequency to a generated output frequency and adjusting the output frequency to match the reference frequency. As the output signal is adjusted by the loop there occurs a point at which the frequencies of the output and reference signals match. At this point the signals are sometimes said to be in frequency lock. When the generated frequency is further synchronized in phase with the input frequency the condition is often referred to as phase lock, the locked state, or simply lock. During lock, when the output frequency is synchronized with the reference frequency, the phase error between the output frequency and reference frequency may be very small or even zero. In the lock state, the output signal will generally stay in lock until the phase lock loop is somehow perturbed. Some common factors that perturb phase lock loops are loss of the reference frequency, a change in the frequency or phase of the reference frequency, noise on the reference frequency, or noise in the system which disturbs the loop.
As shown in background art FIG. 1, a PLL 100 may include a voltage controlled oscillator (VCO) 125 and a reference clock input signal 105. The PLL is completed by feeding back the output of VCO 125 to a phase/frequency detector (PFD) 110 which also receives the reference clock signal 105. More particularly, clock 101 is provided to a divider circuit 102 which divides the clock signal by a value of N. The output of the divider 102 is reference clock signal 105 and is provided as one input to the phase/frequency detector 110. The output of the phase/frequency detector 110 is provided to a charge pump 115 which in turn provides an output to a filter 120. The voltage output of filter 120 is provided to VCO 125 which converts the voltage output of filter 120 to a frequency. The output of the VCO 125 may be provided as an output clock and also utilized in a feedback loop which is provided to divider 130 which divides the output by N. The output of divider 130 is then provided as the second input to phase/frequency detector 110. The M and N values may be called the PLL loop divisors. Therefore, in order to lock to a new frequency, the divide ratio of the loop divisors is changed.
The PLL has found extensive use in mobile communication circuits such as portable telephones. They are used to lock to transmitting and receiving frequencies and to recover clock signals from different digital data formats such as return to zero (RZ) and non return to zero (NRZ). For example, RF radio requires locking to new frequency channels (frequency hopping). Specifically, frequency hopping may be utilized to ensure that interference between communications devices is minimized. That is, if two or more devices are broadcasting on the same frequency destructive interference may occur which may result in a loss of some or all data being broadcast. Therefore, by xe2x80x9choppingxe2x80x9d through many frequencies the probability of running into another device operating on the same frequency is limited. In addition, any encounter with another device operating on the same frequency will only occur until the next xe2x80x9chop.xe2x80x9d
One problem with the PLL is power consumption. Specifically, in a communications device, especially a mobile communications device relying on a battery source, an operational PLL has a large energy requirement and may consume a large portion of the power supplied by the battery. Therefore, several approaches have been used to minimize the rate of power consumption by these mobile communications devices in general, and the PLL in particular.
One approach for minimizing the power draw of the PLL is to enable operation of PLL circuitry only part of the time instead of continuously. For example, as shown in FIG. 1, between locks, the power source (e.g., PUI 145) driving the PLL may be powered down. The length of time of the power down depends on the package being utilized. For example, if a keyboard or mouse is being used to send wireless information, the power down time may be until the next set of information is ready to be sent. Then, when a frequency xe2x80x9chopxe2x80x9d is required, the power up signal utilizes PUI 145 to reestablish the operation of the components within PLL 100.
However, the timeframe for powering up and stabilizing the PLL is extremely crucial to PLL re-activation due to the short lock time specification. One deleterious effect of powering up the PLL is that during power up the logic may transfer faulty pump signals. For example, the transfer of faulty pump signals may result in the components within the PLL sending incorrect information regarding frequency adjustment direction, such as sending an increase frequency signal instead of a decrease frequency signal.
In one conventional approach, the PLL is reactivated from a complete power down state and a constant period of time is waited before power is returned to all components so that all internal signals stabilize before the PLL is functional. This approach is disadvantageous because too much time is lost waiting for signal stabilization. In another approach, an advanced signal powers up the PLL before it is actually needed. This approach consumes too much power for battery operated devices.
In each of these approaches, power-up simulations are utilized to set up the time needed for reactivation. However, modeling error, simulation error, and/or unpredictable delay errors may cause the circuit to fail.
Thus, a need exists for a method for reducing the power up time of a phase lock loop (PLL). A further need exists for a method for reducing the power up time of a PLL which can efficiently reduce power consumption of the PLL. A further need exists for a method for reducing the power up time of a PLL which allows no information to be sent while powering up the PLL until the components within the PLL are stabilized. Still another need exists for a method for reducing the power up time of a PLL which is compatible with existing PLL processes.
A method and circuit for reducing the power up time of a phase lock loop is disclosed. In one embodiment, the present invention cuts off a first voltage to the phase lock loop thereby powering down the phase lock loop. In power down, a second voltage is utilized to maintain the power requirements of the filter node within the phase lock loop while the phase lock loop is otherwise powered down. The PLL is now in an energy conservation mode. The present invention then restores the first voltage to the phase lock loop. A period is waited until the internal components of the PLL stabilize and then the second voltage is disengaged from the filter node wherein the phase lock loop is powered up to operational power.
The present invention provides, in various embodiments, methods for reducing the power up time of a phase lock loop (PLL). Embodiments of the present invention also provide a method for reducing the power up time of a PLL which can efficiently reduce power consumption of the PLL. The present invention further provides a method for reducing the power up time of a PLL which allows no information to be sent while powering up the PLL until the components within the PLL are stabilized. The present invention also provides a method for reducing the power up time of a PLL which is compatible with existing PLL processes. The present invention further provides a method that can be integrated into a design or work with an existing PLL (e.g., modular).
More specifically, in one embodiment, upon PLL power down, the filter node is maintained with a reference voltage. Upon power up, a new frequency is programmed into the PLL. A start signal is then given which powers up the remaining circuits of the PLL, except for the filter node. After a first duration, the reference voltage is disengaged from the filter node. The first duration can be measured based on a predetermined time period obtained, for instance, from trial and error or by a simulation. Alternatively, the first duration could be measured by a signal that indicates that the other circuits are powered up. After the reference voltage is removed, the PLL is operational.